Switching regulators are commonly used in many communication devices for providing one or more regulated supply voltages with high efficiency. In communication devices including low-noise radio-frequency (RF) and analog circuits, which are less tolerant to digital noise, the switching regulator has to be followed by a low-dropout (LDO) voltage regulator. The LDO voltage regulator can eliminate much of the ripples in the switching regulator output and provides a clean supply for the RF and/or analog circuitry. Conventional voltage regulators, which use a PMOS as the pass transistor, can achieve low-dropout operation, and show good power efficiency. However, the PMOS pass transistor presents low impedance to the power supply, and the conventional voltage regulators may have poor performance with respect to power supply rejection (PSR) at high frequencies, where the loop gain drops to near or less than 0 dB.
Traditional solutions also tend to have slow settling time, which can limit the power-up and power-down time of the RF and/or analog circuitry. The settling time is decided by the unity-gain bandwidth (UGB) of the loop. The higher the UGB the lower is the settling time. For stability reasons, the UGB has to be lower than the non-dominant pole (Pnd) of the transfer function of the loop. In conventional LDO voltage regulators, the high output impedance of the PMOS pass transistor leads to a low Pnd as well as a low UGB, which result in long settling times. Some of the existing LDO voltage regulator designs, which use native devices as the pass transistor, may suffer from poor power efficiency and may not be compatible with advanced processes such as 16 nano-meter finFET. Others use charge pumps and RC filters, which results in increased complexity and chip area.